`include "C:\Users\lenovo\Desktop\Files\Linear_RISCV\LR_ver_0\src\include\include.vh"

module ex_ls_u(
    input				clk,
    input				rst_n,
    input               flush,
    input				ena,

    input      [3: 0]   exe_type_exu,
    output     [3: 0]   exe_type_lsu,

    input      [63:0]   exu_out_exu,
    output     [63:0]   exu_out_lsu,

    input	   [2: 0]   Load_sel_exu,
    output     [2: 0]   Load_sel_lsu,

    input      [2: 0]   ctrl_bus_exu,
    output     [2: 0]   ctrl_bus_lsu,

    input      [63:0]   Store_data_exu,
    output     [63:0]   Store_data_lsu,

    input      [4: 0]   rd_exu,
    output     [4: 0]   rd_lsu
);
        pip_reg  #(.N(64),.zero(64'd0))
            u_Rs2_reg
                (
                    .clk         (clk),
                    .rst_n     (rst_n),
                    .flush     (flush),
                    .ena         (ena),
                    .data_i  (exu_out_exu),
                    .data_o  (exu_out_lsu)
                );
            
        pip_reg  #(.N(64),.zero(64'd0))
            u_imm_reg
                (
                    .clk         (clk),
                    .rst_n     (rst_n),
                    .flush     (flush),
                    .ena         (ena),
                    .data_i  (Store_data_exu),
                    .data_o  (Store_data_lsu)
                );

        pip_reg  #(.N(3),.zero(3'd0))
        u_Ctrl_bus_reg
            (
                .clk         (clk),
                .rst_n     (rst_n),
                .flush     (flush),
                .ena         (ena),
                .data_i  (ctrl_bus_exu),
                .data_o  (ctrl_bus_lsu)
            );

        pip_reg  #(.N(3),.zero(3'd0))
        u_L_sel_reg
            (
                .clk         (clk),
                .rst_n     (rst_n),
                .flush     (flush),
                .ena         (ena),
                .data_i  (Load_sel_exu),
                .data_o  (Load_sel_lsu)
            ); 

        pip_reg  #(.N(4),.zero(4'd0))
        u_exe_reg
            (
                .clk         (clk),
                .rst_n     (rst_n),
                .flush     (flush),
                .ena         (ena),
                .data_i  (exe_type_exu),
                .data_o  (exe_type_lsu)
            );
        
        pip_reg  #(.N(5),.zero(5'd0))
        u_rd_reg
            (
                .clk         (clk),
                .rst_n     (rst_n),
                .flush     (flush),
                .ena         (ena),
                .data_i     (rd_exu),
                .data_o     (rd_lsu)
            );


endmodule